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STV6688
Video Switch Matrix for TV Applications with S Terminal
PRODUCT PREVIEW
Key Features
s IC Bus Control s Standby Mode s 4 Y/CVBS Inputs (one for internal TV signal) s 4 C Inputs (one for internal TV signal) s 1 Y/C Adder s 1 Y/CVBS and 1 C Output, each with 0 dB gain s 1 CVBS Output with 6 dB gain and 150 Buffer for Monitor s SYNC Bottom Clamp on all CVBS/Y and Average Bias on C Inputs s Bandwidth: 15 MHz s Crosstalk: 50 dB (min.) PSO20 Order Code: STV6688A Order Code: STV6688 PDIP20
General Description
The STV6688 is a highly-integrated IC buscontrolled video switch matrix, optimized for use in color TV applications. It is used to control the switching of 4 video signals. These signals can be in Single Component form (CVBS) or in Two Component form (Y/C). In both cases, the STV6688 microcontroller provides a CVBS signal for an external device (monitor).
Pin Connections
Y/CVBS_IN1 C_IN1 VCC_V Y/CVBS_IN2 C_IN2 GND_V Y/CVBS_IN3 C_IN3 VDD SDA
1 2 3 4 5 6
20 19 18 17 16 15 14 13 12 11
DEC Y/CVBS_IN_TV C_IN_TV VCC_B CVBS_OUT GND_B Y/CVBS_OUT C_OUT GND SCL
7
8 9 10
September 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/12
Functional Description
STV6688
1
Functional Description
Table 1: Pin List
Pin
1 2 3 4 5 6 7 8 9 10
Symbol
Y/CVBS_IN1 C_IN1 VCC_V Y/CVBS_IN2 C_IN2 GND_V Y/CVBS_IN3 C_IN3 VDD SDA
Description
Y or CVBS Signal of Ext. Input 1 C Signal of Ext. Input 1 Video Switch Power Supply Y or CVBS Signal of Ext. Input 2 C Signal of Ext. Input 2 Video Switch Ground Y or CVBS Signal of Ext. Input 3 C Signal of Ext. Input 3 Digital Parts Power Supply Serial Data Line Input
Pin
11 12 13 14 15 16 17 18 19 20
Symbol
SCL GND C_OUT Y/CVBS_OUT GND_B CVBS_OUT VCC B C_IN_TV Y/CVBS_IN_TV DEC
Description
Serial Clock Line Input Digital Parts Ground C Signal Output Y/CVBS Output Buffer Ground Y and C Adder Output Buffer Power Supply C Signal of TV Input Y or CVBS Signal of TV Input Decoupling
Figure 1: STV6688 Block Diagram
Y/CVBS_IN TV 19 Y/CVBS_IN1 Y/CVBS_IN2 Y/CVBS_IN3 1 4 7 0dB 14 Y/CVBS_OUT
+ C_IN TV 18 C_IN1 C_IN2 C_IN3 2 5 8
Clamp
6dB
Buffer
16 CVBS_OUT
Clamp
0dB
Clamp
13 C_OUT
Mute
Clamp
VREF 17 VCC B 3 VDD 9 12 10 GND SDA 11 SCL 15 GND B 6 GND V IC Bus Decoder 20 VCC V DEC
Buffer Power Supply Video Power Supply
2/12
STV6688
Electrical Characteristics
2
Electrical Characteristics
TAMB = 25C, VCCV = VCCB = VDD = 5V, RLoadYC = 4.7 k, RLoadCVBS = 150 , unless otherwise specified.
Symbol VDD VCC VCCB
Parameter
Digital Supply Voltage Video Operating Supply Voltage Buffer Supply Voltage
Test Conditions
Min.
4.5 4.5 4.5
Typ.
5 5 5
Max.
5.5 5.5 5.5
Unit
V V V
Active (Channels ON) IDD ICCV Digital Supply Current Total Video Supply Current (VCC,VCCBi) VDD = 5 V VCC = 5 V, No load VCCV = VCCB = 5V, with loads and signals 3 13 25 mA
mA
Standby (All Channels OFF) IDD ICCVstd Digital Supply Current Total Video Supply Current VDD = 5 V VCC = 5 V 3 0.3 mA mA
2.1
Thermal Data
Parameter
Maximum Junction-to-Ambient Thermal Resistance
Symbol
RthJA
Package
DIP20 (STV6688) SO20 (STV6688A)
Value
80 100
Unit
C/W C/W
2.2
Y/CVBS Section
TAMB = 25C, VCCV = VCCB = VDD = 5V, RLoadYC = 4.7 k, RLoadCVBS = 150 , unless otherwise specified.
Symbol VDCIN ICLAMP ILEAK CIN VIN DYNY DYNCVBS BW
Parameter
DC Input Level Clamping Current Input Leakage Current Input Capacitance Max Input Signal Dynamic Y/CVBS Output Signal Dynamic CVBS Output Signal Bandwidth at -3 dB
Test Conditions
Bottom Sync pulse at VDCIN-400 mV VIN = VDCIN + 1 V
Min.
Typ.
2
Max.
Unit
V mA
1
2 1 2 10
A pF
VCC = 5 V VCC = 5 V VCC = 5 V
1.5 1.5 3
VPP VPP VPP
Y/CVBS VIN = 1 VPP Y/C Mixer (on CVBS_OUT) VIN = 1 VPP
12 8
15 10
MHz
3/12
Electrical Characteristics
Symbol Flatness
STV6688
Test Conditions Min. Typ.
0.2 0.5 55 50 -0.5 5.5 60 55 0 6 2.5 1 VIN = 1 VPP Bottom sync pulse Bottom sync pulse for Y VIN = 1 VPP at f = 4.43 MHz VIN = 1 VPP at f = 4.43 MHz -0.5 0 0.8 1.3 1 1 0.6 Refer to Note 1 65 3 5 3 +0.5 6.5 5.0 5 +0.5
Parameter
Max.
0.5 1.0
Unit
dB
Spread of Gain in Video Band (15 kHz-5 MHz) Y/CVBS VIN = 1 VPP Y/C Mixer (on CVBS_OUT) VIN = 1 VPP Crosstalk Isolation between Y/CVBS Input Channels Crosstalk Isolation of Y/CVBS from C Channels Gain at Y/CVBS out @1 MHz Gain at CVBS out @1 MHz Y/CVBS Output Resistance CVBS Output Resistance Gain matching between Y, CVBS inputs DC CVBS Output voltage DC Y Output voltage Differential Phase Differential Gain Luminance non-linearity Video S/N ratio VIN = 1 VPP at f = 4.43 MHz, on one point. VIN = 1 VPP at f = 4.43 MHz, on one point. VIN = 1 VPP VIN = 1 VPP
CTi CTo GYCVBS GCVBS ROUTY ROUTCVBS GYCVBSM DCOUTCVBS DCOUTY DPHI DG LNL VSN
dB dB dB dB dB V V deg % % dB
Note: 1 S/N = 20log (VOUT Black to White = 0.7 VPP/VNoise (mVRMS) weighted CCIR567).
2.3
Chroma Section
TAMB = 25C, VCCV = VCCB = VDD = 5V, RLoadYC = 4.7 k, RLoadCVBS = 150 , unless otherwise specified.
Symbol VDCIN RIN CIN VIN DYN CBW CTi CTo ROUT GOUTC DCOUTC
Parameter
DC Input Level Input Resistance Input Capacitance Max Input Signal Dynamic Output Signal Chroma Bandwidth Crosstalk Isolation between C Input Channels Crosstalk Isolation of C from Y Channels Output Resistance Gain at C_OUT @4.43 MHz DC Output voltage
Test Conditions
Min.
Typ.
3
Max.
Unit
V k pF
30
50 2 1.5 1.5
VPP VPP MHz dB dB
CIN= 1 VPP CIN = 0. 5VPP at f = 4.43 MHz, on one point. VIN = 1 VPP at f = 4.43 MHz, on one point.
10 55 50
12 60 55 2.5 5.0 +0.5
dB V
VIN = 1 VPP
-0.5
0 2.2
4/12
STV6688
Symbol GCM CToYdel
Electrical Characteristics
Parameter
Gain matching between C inputs Chroma to Luma delay, Y/C source
Test Conditions
VIN = 1 VPP VPP @4.43 MHz
Min.
-0.5
Typ.
0 5
Max.
+0.5 10
Unit
dB ns
5/12
Electrical Characteristics
STV6688
2.4
IC Bus Characteristics
TAMB = 25C, VCCV = VCCB = VDD = 5V, RLoadYC = 4.7 k, RLoadCVBS = 150 , unless otherwise specified.
Symbol Address Selection Input ADDsel_L ADDsel_H ILEAK SCL VIL VIH ILI SDA VIL VIH ILI CI tR tF VOL tF CL
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Address Selection Low Level Address Selection High Level Leakage Current 2.5
0
0.2 VDD 10
V V A
Low Level Input Voltage High Level Input Voltage Input Leakage Current VIN = 0 to 5.5 V
-0.3 3 -10 0
1.5 5.5 10
V V A
Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance 1.5 V to 3 V 3 V to 1.5 V IOL = 3 mA 3 V to 1.5 V VIN = 0 to 5.5 V
-0.3 3 -10 0
1.5 5.5 10 10 1 300 0.4 250 400
V V A pF s ns V ns pF
Timing (Clock Frequency = 100 kHz, see Note 2) tLOW tHIGH tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA Clock Low Period Clock High Period Data Setup Time Data Hold Time Setup Time from Clock High to Stop Start Setup Time following a Stop Start Hold Time Start Setup Time following Clock Low to High Transition 4.7 4 250 0 4 4.7 4 4.7 340 s s ns ns s s s s
Note: 2 The device can also operate at 400 kHz.
6/12
STV6688
Electrical Characteristics
Figure 2: IC Bus Timings
SDA
t BUF t LOW tf
SCL
t HD,STA tr t HD,DAT t HIGH t SU,DAT
SDA (Start, Stop)
t SU,STA t SU,STO
2.5
IC Bus Selection
Data transfers follow the usual IC format: after the Start condition (S), a 7-bit slave address is sent, followed by an 8-bit word which is a data direction bit (W). An 8-bit sub-address is sent to select a register, followed by an 8-bit data word to be included in the register.
S SLAVE ADDRESS: 94h
The IC Bus Decoder of the microcontroller provides the Automatic Incrementation mode in Write mode.
String Format: Write Only mode (S = Start condition, P = Stop condition, A = Acknowledge)
A
00h
A
DATA
A
P
Input Signals Summary: (Write
Reg.Addr. (Hex)
Mode)
Data
D7
General Stand-by
D6
Buffer Stand-by
D5
Always set to 1
D4
D3
D2
D1
D0
Switch Control
Input Signal: (Write Mode) Data Byte
Reg. Addr.
0x00
Data Description
General Stand-by Buffer Stand-by Y/CVBS and C Selection
Bits D7
1 1 2 0 1 X X X X X X
Comments D6
X X 0 1 X X X X
D5
1 1 1 1 1 1 1 1
D4
X X X X X X X X
D3
X X X X X X X X
D2
X X X X X X X X
D1
X X X X 0 0 1 1
D0
X X X X 0 1 0 1 All disabled All active Buffer disabled Buffer active INT TV IN1 IN2 IN3
7/12
Input/Output Groups
STV6688
3
Input/Output Groups
Figure 3: Bottom Clamped Video Inputs (Pins 1, 4, 7 and 19)
VCC 5 V
VCC 5 V
2 V + VD
15 k tri Protected Pad
Figure 4: Average Clamped Video Inputs (Pins 2, 5, 8 and 18)
VCC 5 V VCC 5 V IB 25 k 25 k 3V
tri
Protected Pad
Figure 5: Video Outputs (Pins 13, 14 and 16)
VCC 5 V
V CCB1,2 ...7 5 V
IB
Protected Pad
8/12
STV6688
Figure 6: IC Bus SDA (Pin 10)
Input/Output Groups
VDD 5 V
Float Acknowledge 10 k
Protected Pad
Figure 7: IC Bus SCL (Pin 11)
V DD 5 V
Float
10 k
Protected Pad
9/12
Package Mechanical Data
STV6688
4
Package Mechanical Data
Figure 8: 20-Pin Plastic Single in Line Package (PDIP20)
mm Dim. Min.
A A1 A2 b b2 c D e E1 L 6.10 2.92 0.38 2.92 0.36 1.14 0.20 24.89 2.54 6.35 3.30 7.11 3.81 0.240 0.115 3.30 0.46 1.52 0.25 4.95 0.56 1.78 0.36 26.92
Inches Max.
5.33 0.015 0.115 0.014 0.045 0.008 0.980 0.100 0.250 0.130 0.280 0.150 0.130 0.018 0.060 0.010 0.195 0.022 0.070 0.014 1.060
Typ.
Min.
Typ.
Max.
0.210
10/12
STV6688
Package Mechanical Data
Figure 9: 20-Pin Plastic Small Outline Package, 300-mil Width (PSO20)
mm Dim. Min.
A A1 B C D E e H h K L G N 10.01 0.25 0 0.41 4.98 7.40 1.27 10.64 0.74 8 1.27 0.10 Number of Pins 20 0.394 0.010 0 0.016 2.35 0.10 0.33 0.51 0.32 13.00 7.60 0.1961 0.2914
Inches Max.
2.65
Typ.
Min.
0.0926 0.0040 0.0130
Typ.
Max.
0.1043 0.0200 0.0125 0.5118 0.2992
0.050 0.419 0.029 8 0.050 0.004
11/12
Package Mechanical Data
STV6688
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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